Pre-cutting a back side of a silicon substrate for growing better iii-v group compound layer on a front side of the substrate

ABSTRACT

The present disclosure involves an apparatus. The apparatus includes a substrate having a front side a back side opposite the front side. The substrate includes a plurality of openings formed from the back side of the substrate. The openings collectively define a pattern on the back side of the substrate from a planar view. In some embodiments, the substrate is a silicon substrate or a silicon carbide substrate. Portions of the silicon substrate vertically aligned with the openings have vertical dimensions that vary from about 100 microns to about 300 microns. A III-V group compound layer is formed over the front side of the silicon substrate. The III-V group compound layer is a component of one of: a light-emitting diode (LED), a laser diode (LD), and a high-electron mobility transistor (HEMT).

PRIORITY DATA

The present application is a divisional application of U.S. patentapplication Ser. No. 13/616,415, filed on Sep. 14, 2012, the disclosureof which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to III-V group compounddevices, and more particularly, to improving the growth of III-V groupcompound layers on a substrate.

BACKGROUND

The semiconductor industry has experienced rapid growth in recent years.Technological advances in semiconductor materials and design haveproduced various types of devices that serve different purposes. Thefabrication of some types of these devices may require forming one ormore III-V group compound layer on a substrate, for example forming agallium nitride layer on a substrate. Devices using III-V groupcompounds may include light-emitting diode (LED) devices, laser diode(LD) devices, radio frequency (RF) devices, high electron mobilitytransistor (HEMT) devices, and/or high power semiconductor devices.

Traditionally, manufacturers have formed the III-V group compound layeron a sapphire substrate. However, sapphire substrates are expensive.Thus, some manufacturers have been attempting to form III-V groupcompound layers on a silicon substrate, which is cheaper. However, dueto lattice constant mismatches and the different thermal expansioncoefficients between the III-V group compound layer and the siliconsubstrate, existing methods of forming a III-V group compound layer on asilicon substrate may result in wafer defects (e.g., cracking defects)or yield low quality III-V group compound layers.

Therefore, while existing methods of forming III-V group compound layerson silicon substrates have been generally adequate for their intendedpurposes, they have not been entirely satisfactory in every aspect. Amethod of growing high quality III-V group compound layers on a siliconlayer without defects such as cracking continues to be sought.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIGS. 1-2 are diagrammatic fragmentary cross cross-sectional side viewsof an example substrate processed according to various aspects of thepresent disclosure.

FIGS. 3-8 are diagrammatic planar views of a back side of a substrateprocessed according to various aspects of the present disclosure.

FIGS. 9-11 are diagrammatic fragmentary cross cross-sectional side viewsof example light-emitting diodes (LEDs) according to various aspects ofthe present disclosure.

FIG. 12 is a diagrammatic fragmentary cross-sectional side view of anexample LED lighting apparatus according to various aspects of thepresent disclosure.

FIG. 13 is a diagrammatic view of a lighting module that includes theLED lighting apparatus of FIG. 12 according to various aspects of thepresent disclosure.

FIG. 14 is a diagrammatic fragmentary cross cross-sectional side view ofan example laser diode (LD) according to various aspects of the presentdisclosure.

FIG. 15 is a diagrammatic fragmentary cross cross-sectional side view ofan example high electron mobility transistor (HEMT) according to variousaspects of the present disclosure.

FIG. 16 is a flowchart illustrating a method of processing a substrateto improve the quality of one or more III-V group compound layer grownthereon according to various aspects of the present disclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of variousembodiments. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. Moreover, the terms “top,” “bottom,” “under,” “over,”and the like are used for convenience and are not meant to limit thescope of embodiments to any particular orientation. Various features mayalso be arbitrarily drawn in different scales for the sake of simplicityand clarity. In addition, the present disclosure may repeat referencenumerals and/or letters in the various examples. This repetition is forthe purpose of simplicity and clarity and does not in itself necessarilydictate a relationship between the various embodiments and/orconfigurations discussed.

As semiconductor fabrication technologies continue to advance, III-Vgroup compound materials have been utilized to produce a variety ofdevices, such as light-emitting diode (LED) devices, radio frequency(RF) devices, high electron mobility transistor (HEMT) devices, and highpower semiconductor devices. A III-V group compound material includes acompound that contains an element from a “III” group (or family) of theperiodic table, and another element from a “V” group (or family) of theperiodic table. For example, the III group elements may include Boron,Aluminum, Gallium, Indium, and Titanium, and the V group elements mayinclude Nitrogen, Phosphorous, Arsenic, Antimony, and Bismuth.

Traditionally, III-V group compound materials have been grown onsapphire substrates. However, sapphire substrates are expensive. Incomparison, silicon substrates are cheaper and have been used as thesubstrate on which semiconductor devices are formed for many years.Hence, it is desirable to use silicon substrates as the substrates forgrowing III-V group compound materials. Unfortunately, a significantlattice mismatch exists between a III-V group compound materials and asilicon substrate. In addition, the III-V group compound materials andthe silicon substrate also have different coefficients of thermalexpansion (CTE). Due at least in part to the lattice mismatch and thedifferent CTEs, stress or strain will result between the siliconsubstrate and a III-V group compound layer formed thereon. Such stressor strain can lead to difficulty of growth of the III-V group compoundlayer and/or cracks during fabrication. Some existing methods attempt toresolve these issues have either not been able to adequately prevent thedefects such as cracks, and/or may lead to a degradation of the qualityof the III-V group compound material that is grown on the siliconsubstrate.

According to various aspects of the present disclosure, described belowis a method of forming a high quality III-V group compound layer on asubstrate with substantial defect reduction.

Referring to FIG. 1, a diagrammatic fragmentary cross-sectional sideview of a substrate 20 is illustrated. In the present embodiments, thesubstrate 20 is a silicon substrate. In other embodiments, the substrate20 may be a silicon carbide substrate, a gallium arsenide substrate, ora composite substrate. For the discussions below, the substrate 20 isreferred to as a silicon substrate 20, though it is understood that theconcepts of the present disclosure may apply to the silicon carbidesubstrate, the gallium arsenide substrate, or the composite substrate aswell.

The silicon substrate 20 is a portion of a wafer. Silicon wafers havebeen used for semiconductor fabrication for many years and areinexpensive. Therefore, it is desirable to be able to grow III-V groupcompound layers on a silicon wafer. As shown in FIG. 1, the siliconsubstrate 20 has a front side (or front surface) 22 and a back side 24(or back surface). The III-V group compound layer (and other layers)will be formed over the front side 22 of the silicon substrate 20, forexample through an epitaxial growth process.

Referring now to FIG. 2, the back side 24 of the silicon substrate 20undergoes processing before the III-V group compound layer isepitaxially grown on the front side 22 of the silicon substrate 20. Invarious embodiments, the back side processing of the silicon substrate20 includes forming a plurality of recesses (also referred to asopenings or trenches) 30 in the back side 24 of the silicon substrate20. This back side processing may also be referred to as a back sidepre-cut. In some embodiments, the recesses 30 are formed by a laserprocess. In other embodiments, the recesses 30 may be formed by alithography process, such as an etching process. The recesses 30 followa pattern in a top view, for example a square pattern, a crisscrosspattern (which may include crisscrossing rectangles or crisscrossingtriangles), a concentric circles pattern, a radial pattern, hole or rodpatterns, or other suitable patterns. The top views of some of thesepatterns are shown in FIGS. 3-8. In some embodiments, the recesses 30have substantially identical or substantially similar shapes or sizes.

Still referring to FIG. 2, the recesses 30 effectively form a buffer forthe expansion or contraction of the substrate 20 during variousepitaxial growth processes used to form the layers on the front side 22of the substrate 20. These processes may have varying processtemperatures, and the substrate 20 may also be cooled between some ofthese processes as well. These different temperatures may cause thesubstrate 20 to expand or contract, which may introduce stress for thelayers formed on the front side 22 of the substrate 20. With therecesses 30 in place, the substrate 20 now has more room to expand orcontract, thereby reducing the amount of stress applied to the layersformed on the front side 22.

The portions of the substrate 20 located between adjacent recesses 30have a lateral dimension (or width) 40. In some embodiments, the lateraldimension 40 is less than about 100 microns (um). The range for thelateral dimension 40 is chosen so that the remaining portion of thesubstrate 20 (i.e., after the recesses 30 have been formed therein) canstill have room to contract or expand laterally without causing unduestress for the epi-layers grown on the front side 22 of the substrate 20later.

Also, a remaining portion of the substrate 20 has a vertical dimension(thickness) 50, which is defined as a distance from a front surface(surface facing the front side 22) of the substrate 20 to a bottom ofthe recesses 30. In some embodiments, the vertical dimension 50 is in arange from about 100 um to about 300 um. The range for the verticaldimension 50 is chosen so that the remaining portion of the substrate 20can still provide sufficient mechanical support for growing theepi-layers on the front side 22 of the substrate 20.

The specific geometries for the recesses 30 and the substrate 20 forvarious recess patterns will now be discussed in more detail withreference to FIGS. 3-8, which illustrate planar views (also referred toas birds-eye views of top views). The recesses 30 may also be referredto as scribe lines in the embodiments discussed below.

In the embodiment illustrated in FIG. 3, the recesses 30 define acrisscrossing rectangles pattern on the back side 24 of the substrate20. In other words, the recesses 30 are arranged in a plurality ofintersecting trenches or “lines” across the back side 24 of thesubstrate 20. In this embodiment, the intersecting recesses 20 aresubstantially perpendicular to one another. Thus, the back side 24 ofthe substrate 20 is divided into a plurality of “island-like” rectangles20A. The rectangles have a horizontal dimension 40A and a verticaldimension 40B in the planar view shown in FIG. 3. It is understood thatboth the horizontal dimension 40A and the vertical dimension 40B aremanifestations of the lateral dimension 40 discussed above and shown inFIG. 2. In some embodiments, the horizontal dimension 40A and thevertical dimension 40B are both in a range from about 1 um to about 100um. The recesses 30 also have a dimension 60 defining a “width” of therecesses. In some embodiments, the dimension 60 of the recesses is in arange from about 10 um to about 100 um.

In the embodiment illustrated in FIG. 4, the recesses 30 define aconcentric circles pattern on the back side 24 of the substrate 20. Inother words, the recesses 30 are arranged in a plurality of circles onthe back side 22 of the substrate 20, wherein a smaller circle islocated within a larger circle, which is located in an even largercircle, so on and so forth. The circles are spaced apart from adjacentcircles by a spacing 40C, which is also a manifestation of the lateraldimension 40 discussed above and shown in FIG. 2. In some embodiments,the spacing 40C is in a range from about 1 um to about 100 um. Thecircles also each have a “line width”, which is the same as thedimension 60 discussed above that defines a “width” of the recesses 30.In some embodiments, the line width 60 of the recesses is in a rangefrom about 10 um to about 100 um.

In the embodiment illustrated in FIG. 5, the recesses 30 define a holepattern on the back side 24 of the substrate 20. In other words, therecesses 30 are arranged as a plurality of holes on the back side 22 ofthe substrate 20, which may be substantially rounded in someembodiments. The holes are spaced apart from adjacent holes by a spacing40D, which is also a manifestation of the lateral dimension 40 discussedabove and shown in FIG. 2. In some embodiments, the spacing 40D is in arange from about 1 um to about 100 um. The holes also each have a“diameter”, which is the same as the dimension 60 discussed above thatdefines a “width” of the recesses 30. In some embodiments, the diameter60 of the holes is in a range from about 10 um to about 100 um.

In the embodiment illustrated in FIG. 6, the recesses 30 define a rodpattern on the back side 24 of the substrate 20. In other words, therecesses 30 are formed in the back side 24 of the substrate 20 in amanner such that the remaining portions of the substrate 20E form aplurality of rods, which may be substantially rounded in someembodiments. It may be said that the hole pattern shown in FIG. 5 is anopposite of the rod pattern shown in FIG. 6. Stated differently, therounded holes 30 in FIG. 5 are formed by the recesses 30 in thesubstrate 20, whereas the rounded rods 20E in FIG. 6 are formed by theportions of the substrate 20 themselves. The rods are spaced apart fromadjacent rods by a spacing 60, which is the same as the lateraldimension 60 discussed above that defines a “width” of the recesses 30.In some embodiments, the spacing 60 between the adjacent rods is in arange from about 10 um to about 100 um. The rods 20E also each have adiameter 40E, which is a manifestation of the lateral dimension 40discussed above and shown in FIG. 2. In some embodiments, the spacing40E is in a range from about 1 um to about 100 um.

In the embodiment illustrated in FIG. 7, the recesses 30 define a radialpattern on the back side 24 of the substrate 20. In other words, therecesses 30 are arranged in a plurality of trenches that extend radiallyoutwards across the back side 24 of the substrate 20. Each of theseradially-extending trenches intersects with one or more other radiallyextending trenches. Thus, the back side 24 of the substrate 20 isdivided into a plurality of “sectors” 20F. These sectors have angles 65.In some embodiments, the angles 65 are in a range between about 1 degreeand about 90 degrees. The radially-extending trenches also each have a“line width”, which is the same as the dimension 60 discussed above thatdefines a “width” of the recesses 30. In some embodiments, the linewidth 60 of the recesses is in a range from about 10 um to about 100 um.

In the embodiment illustrated in FIG. 8, the recesses 30 define acrisscrossing triangles pattern for the back side 24 of the substrate20. In other words, the recesses 30 are arranged in a plurality ofintersecting trenches or “lines” to define a plurality of triangles 20Gacross the back side 24 of the substrate 20. The triangles have amaximum dimension 40G in the planar view shown in FIG. 8. It isunderstood that the maximum dimension 40G is manifestation of thelateral dimension 40 discussed above and shown in FIG. 2. In someembodiments, the maximum dimension 40G is in a range from about 1 um toabout 100 um. The recesses 30 also have a dimension 60 defining a“width” of the recesses. In some embodiments, the dimension 60 of therecesses is in a range from about 10 um to about 100 um.

FIGS. 9-11 are diagrammatic cross-sectional fragmentary side views forseveral types of devices that can utilize the substrate back sidepre-cutting pattern to help grow better III-V group compound layers onthe front side of the substrate. FIGS. 9 to 11 have been simplified fora better understanding of the inventive concepts of the presentdisclosure.

A horizontal LED device 70 is shown in FIG. 9. The horizontal LED 70includes the substrate 20 in which the plurality of recesses 30 havebeen formed in the back side 24, as discussed above. The substrate 20 isa portion of a silicon wafer. In certain embodiments, before anyepitaxial growth process is performed, the substrate 20 is cleaned byboiling it in a sulfuric acid solution (H₂SO₄:H₂O₂ with a 3:1 ratio) forabout 15 minutes, and then dipping it in a hydrofluoric acid solution(HF: H₂O with a 1:10 ratio) for about 15 seconds to remove native oxideformed on the surface of the substrate 20. After the cleaning process,the silicon substrate 20 is loaded into an epitaxial growth chamber andthen heated to a temperature in a range from about 1000 degrees Celsiusto about 1150 degrees Celsius under an H₂ ambient for about 5 to 10minutes to remove a surface passivation layer.

A buffer layer 72 is then formed over the front side 22 of the substrate20. The buffer layer 72 is formed in an epitaxial growth process. Insome embodiments, the epitaxial growth process has a process temperatureless than about 1200 degrees Celsius. In certain embodiments, the bufferlayer 72 may include a step aluminum (Al) grade-composition buffer,which may contain an aluminum nitride (AlN) layer and a plurality ofaluminum gallium nitride (AlGaN) layers formed over the MN layer, wherethe AlGaN layers have increasing thicknesses the farther they are fromthe substrate 20, and where the aluminum concentration decreases thefarther they are from the substrate. Such buffer layer is described inmore detail in U.S. patent application Ser. No. 13/398,954, withattorney docket number 2011-1496/48047.75, filed on Feb. 17, 2012, andentitled “METHOD OF GROWING A HIGH QUALITY III-V COMPOUND LAYER ON ASILICON SUBSTRATE,” the contents of which are hereby incorporated byreference in their entirety.

A first gallium nitride (GaN, a type of III-V group compound) layer 74is formed over the buffer layer 72. An MN layer 76 is then formed overthe first GaN layer 74. A second GaN layer 78 is then formed over the MNlayer 76. These layers 74-78 may each be formed by an epitaxial growthprocess.

A doped semiconductor layer 80 is then formed over the second GaN layer78. The doped semiconductor layer 80 is formed by an epitaxial growthprocess known in the art. In the illustrated embodiments, the dopedsemiconductor layer 80 is doped with an n-type dopant, for exampleCarbon (C) or Silicon (Si). The doped semiconductor layer 80 includes aIII-V group compound, which is gallium nitride in the presentembodiment. Thus, the doped semiconductor layer 80 may also be referredto as nGaN layer. In some embodiments, the nGaN layer 80 has a thicknessthat is in a range from about 2 um to about 6 um.

A pre-layer 85 is formed over the nGaN layer 80. The pre-layer 85 mayinclude a plurality of pairs of indium gallium nitride (InGaN) andgallium nitride (GaN), for example between about 15 and 25 pairs. The Incontent may be in a range from about 0.1 to about 0.2. A thickness ofthe InGaN is in a range from about 0.5 nm to about 2 nm, and a thicknessof the GaN is in a range from about 1 nm to about 3 nm.

A multiple-quantum well (MQW) layer 90 is formed over the pre-layer 85.The MQW layer 90 includes alternating (or periodic) sub-layers of activematerial, such as gallium nitride and indium gallium nitride (InGaN).For example, the MQW layer 90 may include a number of gallium nitridesub-layers and a number of indium gallium nitride sub-layers, whereinthe gallium nitride sub-layers and the indium gallium nitride sub-layersare formed in an alternating or periodic manner. In one embodiment, theMQW layer 90 includes ten sub-layers of gallium nitride and tensub-layers of indium gallium nitride, where an indium gallium nitridesub-layer is formed on a gallium nitride sub-layer, and another galliumnitride sub-layer is formed on the indium gallium nitride sub-layer, andso on and so forth. Each of the sub-layers within the MQW layer is dopedwith a different type of conductivity from its adjacent sub-layer. Thatis, the various sub-layers within the MQW layer are doped in analternating p-n fashion. The light emission efficiency depends on thenumber of layers of alternating layers and their thicknesses. In someembodiments, the MQW layer 90 has a thickness in a range from about 90nanometers (nm) to about 200 nm. At the top of the MQW layer 90, thereis an InAlGaN last barrier layer, which may have an aluminum contentbetween 0 and 1, and an indium content between 0 and 1, and a thicknessbetween about 7 nm and about 25 nm. This InAlGaN last barrier layer mayor may not be considered a part of the MQW layer 90 and is notspecifically illustrated herein.

An electron blocking layer 100 may optionally be formed over the MQWlayer 90. The electron blocking 100 layer helps confine electron-holecarrier recombination within the MQW layer 90, which may improve quantumefficiency of the MQW layer 90 and reduce radiation in undesiredbandwidths. In some embodiments, the electron blocking layer 100 mayinclude a doped indium aluminum gallium nitride (InAlGaN) material, andthe dopant may include a p-type dopant such as Magnesium. In someembodiments, the electron blocking layer 100 may have an aluminumcontent between 0 and 1, and an indium content between 0 and 1, and athickness between about 10 nm and about 25 nm.

A doped semiconductor layer 110 is formed over the electron blockinglayer 100 (and thus over the MQW layer 90). The doped semiconductorlayer 110 is formed by an epitaxial growth process known in the art. Insome embodiment, the doped semiconductor layer 110 is doped with adopant having an opposite (or different) type of conductivity from thatof the doped semiconductor layer 80. Thus, in the embodiment where thedoped semiconductor layer 80 is doped with an n-type dopant, the dopedsemiconductor layer 110 is doped with a p-type dopant. The dopedsemiconductor layer 110 includes a III-V group compound, which is agallium nitride compound in the illustrated embodiments. Thus, the dopedsemiconductor layer 110 may also be referred to as a pGaN layer. In someembodiments, the pGaN layer 110 has a thickness that is in a range fromabout 150 nm to about 200 nm.

A core portion of the LED 70 is created by the disposition of the MQWlayer 90 between the nGaN layer 80 and the pGaN layer 110. When anelectrical voltage (or electrical charge) is applied to the doped layersof the LED 70, the MQW layer 90 emits radiation such as light. The colorof the light emitted by the MQW layer 90 corresponds to the wavelengthof the radiation. The radiation may be visible, such as blue light, orinvisible, such as ultraviolet (UV) light. The wavelength of the light(and hence the color of the light) may be tuned by varying thecomposition and structure of the materials that make up the MQW layer90.

Additional processes may be performed to complete the fabrication of theLED 70. For example, an electrically-conductive contact layer 120 may beformed over the pGaN layer 110. A portion of the layer 80 is etched awayso that a part of nGaN layer 80 is exposed. Metal contacts 130-131 maythen be formed on the surface of the exposed nGaN layer 80 and on thesurface of the contact layer 120, respectively. The metal contacts130-131 are formed by one or more deposition and patterning processes.The metal contacts 130-131 allow electrical access to the dopedsemiconductor layer 80 and to the doped semiconductor layer 110,respectively.

The LED 70 discussed above with reference to FIG. 9 pertains to ahorizontal LED. Similarly, a vertical LED may also be fabricated toincorporate the improved MQW layer 90. For example, FIG. 3 illustratesan example of such vertical LED 150. Similar components in the verticaland horizontal LEDs are labeled the same for reasons of consistency andclarity.

Referring to FIG. 10, the vertical LED 150 contains many same materialsas those shown in the horizontal LED 70 of FIG. 9. Thus, similarelements are labeled the same for reasons of clarity and consistency. AnInGaN layer 152 is formed over the pGaN layer 110. The InGaN layer 152may be p-doped or undoped. A bonding metal layer 154 is formed over theInGaN layer 152. Thereafter, a submount 160 is bonded to the bondingmetal layer 154. The submount 160 may contain a ceramic material or asilicon material in various embodiments.

Referring now to FIG. 11, a p-contact layer 170 is formed over thesubmount 160. The p-contact layer 170 may include a metal materialsuitable for conducting electricity. The silicon substrate 20 is alsoremoved by wet etching, for example by a solution containing HF, aceticacid (CH₃COOH), or oxalic acid (HOOC—COOH). The various layers formedbetween the silicon substrate 20 and the nGaN layer 80 may also beremoved, for example by a reactive ion etching process. The removal ofthe silicon substrate 20 is made easier by the recesses 30 formed in theback side 24 of the silicon substrate 20. This is at least in part dueto the fact that the recesses 30 effectively increase the surface areaof the silicon substrate 20. As a result, the wet etching solutions cancome into contact with the silicon substrate 20 more effectively, andtherefore remove the silicon more effectively. In addition, the recesses30 correspond to the absence of silicon material in the siliconsubstrate 20, meaning less silicon needs to be etched away. This alsomakes the removal of the silicon substrate 20 easier. Thereafter, one ormore n-contacts 175 are formed on the exposed surface of the nGaN layerfrom the back side. The p-contact layer 170 and the n-contacts 175provide electrical access to the vertical LED 150.

To complete the fabrication of the horizontal LED 70 or the vertical LED150, additional processes such as dicing, packaging, and testingprocesses may also be performed, but they are not illustrated herein forthe sake of simplicity.

The LED 70 (or the LED 150) discussed above may be implemented as a partof a lighting apparatus. For example, the LED 70 (or the LED 150) may beimplemented as a part of a LED-based lighting instrument 300, asimplified cross-sectional view of which is shown in FIG. 12. Theembodiment of the LED-based lighting instrument 300 shown in FIG. 12includes a plurality of LED dies. In other embodiments, the lightinginstrument 300 may include a single LED die.

As discussed above, the LED dies include an n-doped III-V group compoundlayer, a p-doped III-V group compound layer, and a MQW layer disposedbetween the n-doped and p-doped III-V group compound layers. In someembodiments, the LED dies 70 each have a phosphor layer coated thereon.The phosphor layer may include either phosphorescent materials and/orfluorescent materials. The phosphor layer may be coated on the surfacesof the LED dies 70 in a concentrated viscous fluid medium (e.g., liquidglue). As the viscous liquid sets or cures, the phosphor materialbecomes a part of the LED package. In practical LED applications, thephosphor layer may be used to transform the color of the light emittedby an LED dies 70. For example, the phosphor layer can transform a bluelight emitted by an LED die 70 into a different wavelength light. Bychanging the material composition of the phosphor layer, the desiredlight color emitted by the LED die 70 may be achieved.

The LED dies 70 are mounted on a substrate 320. In some embodiments, thesubstrate 320 includes a Metal Core Printed Circuit Board (MCPCB). TheMCPCB includes a metal base that may be made of aluminum (or an alloythereof). The MCPCB also includes a thermally conductive butelectrically insulating dielectric layer disposed on the metal base. TheMCPCB may also include a thin metal layer made of copper that isdisposed on the dielectric layer. In alternative embodiments, thesubstrate 320 may include other suitable thermally conductivestructures. The substrate 320 may or may not contain active circuitryand may also be used to establish interconnections.

The lighting instrument 300 includes a diffuser cap 350. The diffusercap 350 provides a cover for the LED dies 70 therebelow. Stateddifferently, the LED dies 70 are encapsulated by the diffuser cap 350and the substrate 320 collectively. In some embodiments, the diffusercap 350 has a curved surface or profile. In some embodiments, the curvedsurface may substantially follow the contours of a semicircle, so thateach beam of light emitted by the LED dies 70 may reach the surface ofthe diffuser cap 350 at a substantially right incident angle, forexample, within a few degrees of 90 degrees. The curved shape of thediffuser cap 350 helps reduce Total Internal Reflection (TIR) of thelight emitted by the LED dies 70.

The diffuser cap 350 may have a textured surface. For example, thetextured surface may be roughened, or may contain a plurality of smallpatterns such as polygons or circles. Such textured surface helpsscatter the light emitted by the LED dies 70 so as to make the lightdistribution more uniform. In some embodiments, the diffuser cap 350 iscoated with a diffuser layer containing diffuser particles.

In some embodiments, a space 360 between the LED dies 70 and thediffuser cap 350 is filled by air. In other embodiments, the space 360may be filled by an optical-grade silicone-based adhesive material, alsoreferred to as an optical gel. Phosphor particles may be mixed withinthe optical gel in that embodiment so as to further diffuse lightemitted by the LED dies 70.

Though the illustrated embodiment shows all of the LED dies 70 beingencapsulated within a single diffuser cap 350, it is understood that aplurality of diffuser caps may be used in other embodiments. Forexample, each of the LED dies 70 may be encapsulated within a respectiveone of the plurality of diffuser caps.

The lighting instrument 300 may also optionally include a reflectivestructure 370. The reflective structure 370 may be mounted on thesubstrate 320. In some embodiments, the reflective structure is shapedlike a cup, and thus it may also be referred to as a reflector cup. Thereflective structure encircles or surrounds the LED dies 70 and thediffuser cap 350 in 360 degrees from a top view. From the top view, thereflective structure 370 may have a circular profile, a beehive-likehexagonal profile, or another suitable cellular profile encircling thediffuser cap 350. In some embodiments, the LED dies 70 and the diffusercap 350 are situated near a bottom portion of the reflective structure370. Alternatively stated, the top or upper opening of the reflectivestructure 370 is located above or over the LED dies 70 and the diffusercap 350.

The reflective structure 370 is operable to reflect light thatpropagates out of the diffuser cap 350. In some embodiments, the innersurface of reflective structure 370 is coated with a reflective film,such as aluminum, silver, or alloys thereof. It is understood that thesurface of the sidewalls of the reflective structure 370 may be texturedin some embodiments, in a manner similar to the textured surface of thediffuser cap 350. Hence, the reflective structure 370 is operable toperform further scattering of the light emitted by the LED dies 70,which reduces glare of the light output of the lighting instrument 300and makes the light output friendlier to the human eye. In someembodiments, the sidewalls of the reflective structure 370 have a slopedor tapered profile. The tapered profile of the reflective structure 370enhances the light reflection efficiency of the reflective structure370.

The lighting instrument 300 includes a thermal dissipation structure380, also referred to as a heat sink 380. The heat sink 380 is thermallycoupled to the LED dies 70 (which generate heat during operation)through the substrate 320. In other words, the heat sink 380 is attachedto the substrate 320, or the substrate 320 is located on a surface ofthe heat sink 380. The heat sink 380 is configured to facilitate heatdissipation to the ambient atmosphere. The heat sink 380 contains athermally conductive material, such as a metal material. The shape andgeometries of the heat sink 380 are designed to provide a framework fora familiar light bulb while at the same time spreading or directing heataway from the LED dies 70. To enhance heat transfer, the heat sink 380may have a plurality of fins 390 that protrude outwardly from a body ofthe heat sink 380. The fins 390 may have substantial surface areaexposed to ambient atmosphere to facilitate heat transfer.

FIG. 13 illustrates a simplified diagrammatic view of a lighting module400 that includes some embodiments of the lighting instrument 300discussed above. The lighting module 400 has a base 410, a body 420attached to the base 410, and a lamp 430 attached to the body 420. Insome embodiments, the lamp 430 is a down lamp (or a down light lightingmodule). The lamp 430 includes the lighting instrument 300 discussedabove with reference to FIG. 12. The lamp 430 is operable to efficientlyproject light beams 440. In addition, the lamp 430 can offer greaterdurability and longer lifetime compared to traditional incandescentlamps.

The discussions above illustrate how pre-cutting the back side of asilicon substrate reduces stress and allows for better III-V groupcompound layer epi-growth on the silicon substrate. Though LEDs are usedas an example for a scenario where III-V group compound (e.g., GaN) isgrown on the silicon substrate, the same concept can be applied to laserdiodes (LD) as well, since an LD also benefit from better epi-growth ofIII-V group compounds on a silicon substrate. FIG. 14 illustrates asimplified cross-sectional side view of an embodiment of an LD 500according to various aspects of the present disclosure.

The LD 500 includes a substrate 20, which is a silicon substrate in theembodiment shown. As discussed above, a plurality of recesses 30 areformed in the back side 24 of the silicon substrate 20 to reduce stress,so that III-V group compound layers can be grown on the front side 22 ofthe silicon substrate with reduced stress and reduced cracking.

A III-V group compound layer 520 is formed over the substrate 20 on thefront side 22. In some embodiments, the III-V group compound layer 520includes AlN. Another III-V group compound layer 530 is formed over theIII-V group compound layer 20. In some embodiments, the III-V groupcompound layer 530 includes a plurality of sub-layers, for example AlGaNsub-layers. The thicknesses for these sub-layers may increase, and thealuminum content for these sub-layers may decrease, as the sub-layer goup (i.e., farther away from the substrate 20).

A III-V group compound epi layer 540 is then formed over the III-V groupcompound layer 530. In some embodiments, the III-V group compound epilayer 540 may include GaN. Thereafter, an AlN layer or an AlGaN layer550 is formed over the III-V group compound epi layer 540. Another III-Vgroup compound epi layer 560 is then formed over the AlN or AlGaN layer550.

An n-doped III-V group compound layer 570 is then formed over the III-Vgroup compound epi layer 560. In some embodiments, the n-doped III-Vgroup compound layer 570 includes n-type doped GaN. A plurality of otherlayers 580 may be formed over the n-doped III-V group compound layer570, for example including an n-doped InGaN layer, a cladding layercontaining n-doped InAlGaN, and a guiding layer containing n-dopedInGaN.

Thereafter, a MQW layer 585 may be formed over the layer 580 (and overthe n-doped III-V group compound layer 570). The MQW layer 585 includesinterleaving barrier layers and active layers, for example interleavingInGaN and GaN layers.

An electron blocking layer 590 is formed over the MQW layer 90. In someembodiments, the electron blocking layer 590 includes p-doped InAlGaN.Thereafter, a guiding layer 600 is formed over the electron blockinglayer 590. In some embodiments, the guiding layer 600 includes a p-dopedInGaN. A cladding layer 610 is then formed over the guiding layer. Insome embodiments, the cladding layer 610 includes a p-doped InAlGaN. Ap-doped III-V group compound layer 620 is then formed over the claddinglayer 610. In some embodiments, the p-doped III-V group compound layer570 includes p-type doped GaN.

The various layers of the LD 500 discussed above and shown in FIG. 14are merely example layers. Other LDs may incorporate different layersdepending on the design needs. In addition, other devices such as highelectron mobility transistor (HEMT) devices may also benefit from thestress reduction by pre-cutting the back side of the silicon substrate,so that III-V compounds can be better grown on the front side of thesilicon substrate. For the sake of providing an example, FIG. 15 shows asimplified cross-sectional view of an HEMT device 700. The HEMT device700 shares some similar layers with the LD 500 discussed above.Therefore, similar layers are labeled the same for reasons of clarityand consistency.

Referring to FIG. 15, the HEMT device 700 includes a substrate 20, whichis a silicon substrate in the embodiment shown. As discussed above, aplurality of recesses 30 are formed in the back side 24 of the siliconsubstrate 20 to reduce stress, so that III-V group compound layers canbe grown on the front side 22 of the silicon substrate with reducedstress and reduced cracking.

A III-V group compound layer 520 is formed over the substrate 20 on thefront side 22. In some embodiments, the III-V group compound layer 520includes AlN. Another III-V group compound layer 530 is formed over theIII-V group compound layer 20. In some embodiments, the III-V groupcompound layer 530 includes a plurality of sub-layers, for example AlGaNsub-layers. The thicknesses for these sub-layers may increase, and thealuminum content for these sub-layers may decrease, as the sub-layer goup (i.e., farther away from the substrate 20).

A III-V group compound epi layer 540 is then formed over the III-V groupcompound layer 530. In some embodiments, the III-V group compound epilayer 540 may include GaN. Thereafter, an AlN layer or an AlGaN layer550 is formed over the III-V group compound epi layer 540. Another III-Vgroup compound epi layer 560 is then formed over the AlN or AlGaN layer550.

An un-doped III-V group compound layer 710 is formed on the III-V groupcompound epi layer 560. Thereafter, an aluminum gallium nitride(Al_(x)Ga_(1-x)N) layer 720 is formed over the un-doped III-V groupcompound layer 710. In some embodiments, x is greater than 0 but lessthan 1. Additional processing may be needed to complete the fabricationof the HEMT device 700, but they are not discussed herein for reasons ofsimplicity.

FIG. 16 is a flowchart illustrating a simplified method 800 of growing ahigh quality III-V group compound layer over a silicon substrate. Themethod 800 includes a step 810, in which a silicon substrate isprovided. The silicon substrate has a front side and a back sideopposite the front side.

The method 800 includes a step 820, in which a plurality of openings orrecesses is formed in the back side of the silicon substrate. Theopenings extend from the back side toward the front side. The openingsalso collectively define a pattern on the back side of the siliconsubstrate from a planar view. In various embodiments, the patternincludes one of: a crisscrossing rectangles pattern, a crisscrossingtriangles pattern, a concentric circles pattern, a multiple-holespattern, a multiple-rods pattern, and a radial pattern. The step 820 inperformed before the silicon substrate is loaded into an epitaxialgrowth chamber. In some embodiments, the openings are formed by anetching process. In some other embodiments, the openings are formed by alaser cutting process. In various embodiments, a thickness of aremaining portion of the silicon substrate having no openings is in arange from about 100 microns to about 300 microns. In some embodiments,a lateral dimension of each of the openings is in a range from about 10microns to about 100 microns.

The method 800 includes a step 830, in which a III-V group compoundlayer is grown over the front side of the silicon substrate in anepitaxial growth process. In some embodiments, the III-V group compoundlayer is epitaxially grown directly on a surface of the siliconsubstrate from the front side. In various embodiments, the III-V groupcompound layer is a part of a LED, or a part of a LD, or a part of aHEMT. The LED, LD, HEMT may be formed over the front side of the siliconsubstrate and may each contain a plurality of other III-V group compoundlayers.

Additional processes may be performed before, during, or after theblocks 710-730 discussed herein to complete the fabrication of thephotonic device. For example, in some embodiments, a cleaning processmay be performed to the silicon substrate before the III-V groupcompound layer is grown. The cleaning process may include boiling thesilicon substrate in a sulfuric acid (H₂SO₄:H₂O₂) solution; andthereafter dipping the silicon substrate in a hydrofluoric acid (HF)solution. Other additional processes are not discussed in detail hereinfor reasons of simplicity.

The embodiments of the present disclosure discussed above offeradvantage over existing art. However, it is understood that not alladvantages are necessarily described herein, other embodiments may offerdifferent advantages, and that no particular advantage is required forall embodiments.

One of the advantages is that by precutting the silicon substrate fromthe back side, the recesses formed on the back side can effectivelyreduce the stress for the III-V group compounds grown on the front sideof the silicon substrate. This is at least in part due to the fact thatthe recesses allow the substrate to better absorb stress (e.g., stresscreated during thermal processes) by expanding and contracting with therecesses as a buffer. In comparison, many traditional processes offorming III-V group compound layers on silicon use no cutting of thesilicon substrate at all, which in turn leads to poor growth of theIII-V group compound. In some cases, attempts have been made to pre-cutthe silicon substrate from the front side. However, the drawbacks fromsuch approach include difficult alignment issues for subsequentphotolithography processes, a need to fabricate specific photomasks thatcannot be readily adapted for use for other processes, and a probabilityof a melt back etching phenomenon due to the exposure of III-V compoundmaterials during processing. These problems can all be avoided by theembodiments of the present disclosure, since the embodiments of thepresent disclosure involve pre-cutting the silicon substrate from itsback side.

Another advantage of the present disclosure is that by pre-cutting thesilicon substrate on the back side, it is easier to remove the siliconsubstrate by wet etching when the silicon substrate needs to be removed(for example in the case of the vertical LED shown in FIG. 11). This isat least in part due to the fact that the silicon substrate has agreater surface area and can come into contact with more etchantsolutions, and also that the recesses in the silicon substrate entailsthat a smaller amount of silicon material needs to be removed.

Yet another advantage of the present disclosure is that it is compatiblewith standard fabrication processes, which saves fabrication time andreduces fabrication cost.

One aspect the present disclosure involves a device. The deviceincludes: a silicon substrate having a first surface and a secondsurface opposite the first surface, wherein the silicon substratecontains a plurality of recesses that extend from the second surfacetoward the first surface, and wherein a distance from bottom surfaces ofthe recesses to the first surface of the silicon substrate is in a rangefrom about 100 microns to about 300 microns; and a III-V group compoundlayer formed over the first surface of the silicon substrate.

In some embodiments, the III-V group compound layer is a part of one of:a light-emitting diode (LED), a laser diode (LD), and a high-electronmobility transistor (HEMT). In some embodiments, the device includes alighting module that uses the LED as its light source.

In some embodiments, the III-V group compound layer is in direct contactwith the first surface of the silicon substrate.

In some embodiments, the recesses have substantially similar shapes orsizes.

In some embodiments, the plurality of recesses are arranged so that thesecond surface of the substrate has a predefined pattern from a topview. In some embodiments, the predefined pattern is one of: acrisscrossing rectangles pattern, a crisscrossing triangles pattern, aconcentric circles pattern, a multiple-holes pattern, a multiple-rodspattern, and a radial pattern.

In some embodiments, the recesses include elongate trenches each havinga trench width from about 10 microns to about 100 microns.

Another one aspect the present disclosure involves an apparatus. Theapparatus includes: a silicon substrate having a front side a back sideopposite the front side, wherein the silicon substrate includes aplurality of openings formed from the back side of the siliconsubstrate, and wherein the openings collectively define a pattern on theback side of the silicon substrate from a planar view, and whereinportions of the silicon substrate vertically aligned with the openingshave vertical dimensions that vary from about 100 microns to about 300microns; and a III-V group compound layer formed over the front side ofthe silicon substrate, wherein the III-V group compound layer is acomponent of one of: a light-emitting diode (LED), a laser diode (LD),and a high-electron mobility transistor (HEMT).

In some embodiments, the III-V group compound layer comes into physicalcontact with the silicon substrate from the front side.

In some embodiments, the openings have substantially similar shapes orsizes.

In some embodiments, the pattern defined by the openings on the backside of the silicon substrate is one of: a crisscrossing rectanglespattern, a crisscrossing triangles pattern, a concentric circlespattern, a multiple-holes pattern, a multiple-rods pattern, and a radialpattern.

In some embodiments, the device includes a lighting module that uses theLED as its light source.

In some embodiments, the openings each have a horizontal dimension in arange from about 10 microns to about 100 microns.

Yet another one aspect the present disclosure involves a method ofgrowing a III-V group compound material on a silicon substrate. Themethod includes: forming a plurality of openings in a back side of asilicon substrate, wherein the openings collectively define a pattern onthe back side of the silicon substrate from a planar view; andthereafter growing a III-V group compound layer over a front side of thesilicon substrate in an epitaxial process.

In some embodiments, the method further includes: forming one of: alight-emitting diode (LED), a laser diode (LD), and a high-electronmobility transistor (HEMT) over the front side of the silicon substrate,wherein the III-V group compound layer is a part of one of: the LED, theLD, and the HEMT.

In some embodiments, the growing the III-V group compound layer isperformed so that the III-V group compound layer epitaxially growndirectly on the front side of the silicon substrate. In someembodiments, the method further includes before the growing the III-Vgroup compound layer: boiling the silicon substrate in a sulfuric acid(H₂SO₄:H₂O₂) solution; and thereafter dipping the silicon substrate in ahydrofluoric acid (HF) solution.

In some embodiments, the forming the plurality of openings comprisesetching or laser cutting the openings into the silicon substrate in amanner such that a thickness of a remaining portion of the siliconsubstrate having no openings is in a range from about 100 microns toabout 300 microns, and a lateral dimension of each of the openings is ina range from about 10 microns to about 100 microns.

In some embodiments, the pattern includes one of: a crisscrossingrectangles pattern, a crisscrossing triangles pattern, a concentriccircles pattern, a multiple-holes pattern, a multiple-rods pattern, anda radial pattern.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, comprising: forming a plurality ofrecesses on a first surface of a substrate, the substrate being asilicon substrate or a silicon carbide substrate; and thereafter formingone or more III-V group compound layers over a second surface of thesubstrate, the first surface and the second surface being opposite oneanother.
 2. The method of claim 1, further comprising: forming alattice-buffer layer over the second surface of the substrate, thelattice-buffer layer containing a material that reduces a latticemismatch between a III-V group compound material and silicon or siliconcarbide, wherein the one or more III-V group compound layers are formedover the lattice-buffer layer.
 3. The method of claim 1, furthercomprising: forming one of a light-emitting diode (LED), a laser diode(LD), or a high-electron mobility transistor (HEMT) over the secondsurface of the substrate, wherein the III-V group compound layers arecomponents of the LED, the LD, or the HEMT.
 4. The method of claim 1,wherein the forming of the recesses comprises performing an etchingprocess or a laser cutting process to the first surface of thesubstrate.
 5. The method of claim 1, wherein the recesses collectivelydefine one of the following patterns in a planar view: a crisscrossingrectangles pattern, a crisscrossing triangles pattern, a concentriccircles pattern, a multiple-holes pattern, a multiple-rods pattern, anda radial pattern.
 6. The method of claim 1, wherein the recesses areformed to each have sidewalls and a bottom surface.
 7. The method ofclaim 1, wherein the recesses are formed to be substantially identicalto one another.
 8. The method of claim 1, wherein the recesses areformed to each have a lateral dimension in a range from about 10 micronsto about 100 microns.
 9. The method of claim 1, wherein portions of thesubstrate aligned with the recesses have a thickness range between about100 microns and about 300 microns.
 10. The method of claim 1, furthercomprising: before the forming of the one or more III-V group compoundlayers: boiling the substrate in a sulfuric acid (H₂SO₄:H₂O₂) solution;and thereafter dipping the substrate in a hydrofluoric acid (HF)solution.
 11. A method, comprising: forming, via an etching process or alaser cutting process, a plurality of trenches on a back surface of asubstrate, the substrate being a silicon substrate or a silicon carbidesubstrate; thereafter growing a lattice-buffer layer over the frontsurface of the substrate, the lattice-buffer layer containing a materialthat reduces a lattice mismatch between a III-V group compound materialand silicon or silicon carbide; thereafter forming a light-emittingdiode (LED), a laser diode (LD), or a high-electron mobility transistor(HEMT) over the lattice buffer layer, wherein the forming of the LED,the LD, or the HEMT includes growing a III-V group compound layer overthe lattice-buffer layer.
 12. The method of claim 11, wherein theforming of the trenches is performed such that the trenches collectivelydefine one of the following patterns in a bottom view: a crisscrossingrectangles pattern, a crisscrossing triangles pattern, a concentriccircles pattern, a multiple-holes pattern, a multiple-rods pattern, anda radial pattern.
 13. The method of claim 11, wherein the forming of thetrenches is performed such that: the trenches each have sidewallsurfaces and a bottom surface; and the trenches have substantiallyidentical shapes and sizes.
 14. The method of claim 11, furthercomprising: before the forming of the lattice-buffer layer: boiling thesubstrate in a sulfuric acid (H₂SO₄:H₂O₂) solution; and thereafterdipping the substrate in a hydrofluoric acid (HF) solution.
 15. A methodof growing a III-V group compound material on a substrate, the methodcomprising: forming a plurality of openings in a back side of asubstrate, wherein the openings collectively define a pattern on theback side of the substrate from a planar view; and thereafter growing aIII-V group compound layer over a front side of the substrate in anepitaxial process.
 16. The method of claim 15, further comprising:forming one of: a light-emitting diode (LED), a laser diode (LD), and ahigh-electron mobility transistor (HEMT) over the front side of thesubstrate, wherein the III-V group compound layer is a part of one of:the LED, the LD, and the HEMT.
 17. The method of claim 15, wherein thesubstrate is a silicon substrate, and wherein the growing the III-Vgroup compound layer is performed so that the III-V group compound layerepitaxially grown directly on the front side of the silicon substrate.18. The method of claim 17, further comprising, before the growing theIII-V group compound layer: boiling the silicon substrate in a sulfuricacid (H₂SO₄:H₂O₂) solution; and thereafter dipping the silicon substratein a hydrofluoric acid (HF) solution.
 19. The method of claim 15,wherein the forming the plurality of openings comprises etching or lasercutting the openings into the substrate in a manner such that athickness of a remaining portion of the substrate having no openings isin a range from about 100 microns to about 300 microns, and a lateraldimension of each of the openings is in a range from about 10 microns toabout 100 microns.
 20. The method of claim 15, wherein the patternincludes one of: a crisscrossing rectangles pattern, a crisscrossingtriangles pattern, a concentric circles pattern, a multiple-holespattern, a multiple-rods pattern, and a radial pattern.